Design-Technology Co-Optimization Engineer | Sunnyvale, CA

Detailed Information

  • Location: Santa Clara, CA

  • Company: Intel

So C and IP design teams to understand the Area, Power, Performance, Schedule, and Cost metrics needed to make the product compelling and translate them to process technology requirements. You will partner with tools, library, fabrication, and manufacturing teams to optimize the process to meet product specifications.

You will resolve prototype issues and determine whether problems are design or process-related. You will conduct experiments to identify potential challenges in the process, ensure that the process meets yield, quality, and reliability standards, and drive continuous improvements to enhance the designs, materials, and methodologies. You will design, validate, and characterize

analog building block devices and template cells. You will lead the dissemination of process information to design groups, ensure that it meets future product requirements, and extract necessary technical and device performance data for IP and So C designs.

You will also work on engineering challenges and determine trade-offs to get the best course of action. Qualifications Minimum Qualifications: Candidate must have a Master's Degree or must be a final semester student in a Master's Degree Program with a course or research concentration in areas of semiconductor process and design and their co-optimization.3+months experience with process collateral and its implications to design and/or

manufacturing (yield, process targeting,).3+ months experience with scripting/coding skills and usage of standard tools for data analysis/charting.

Preferred Qualifications: Has industry internship experience or has worked on a design project in college Strong interpersonal and communication skills Exposure to industry simulation and design tools is a plus Requirements listed would be obtained through a combination of industry-relevant job experience, internship experiences, and or schoolwork/classes/research. Inside this Business Group Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.

Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, interaction, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, interactionual orientation, or any other characteristic protected by local law, regulation, or ordinance. Benefits We offer a total compensation package that ranks among the best in the industry.

It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. Annual Salary Range for jobs which could be performed in US, California: $80,190.00-$120,050.00Salary range dependent on a number of factors including location and experience Working Model This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs. Requisition #: JR0252526pca3lyuhf

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